RE: [ethmac] BUSY bit in MIISTATUS

["Igor Mohor\(opencores\)" <igorm@opencores.org>]

Hi, Dennis.

Why is this problem? If you do a read right after the write cycle (that
should change the BUSY bit) it takes more than 2 cycles. However I did
put your changes to the eth_miim.v file.

Thank you for your effort.

Regards,
	Igor

> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]
On
> Behalf Of dennis@microtronix.com
> Sent: Tuesday, May 13, 2003 7:08 PM
> To: ethmac@opencores.org
> Subject: [ethmac] BUSY bit in MIISTATUS
> 
> When using the EMAC to access the MII device, I have noticed that it
> takes a couple of cycles for the BUSY bit to turn on in the MIISTATUS
> register once the command is initiated in the MIICOMMAND register.
> 
> I was wondering if this was the expected behaviour.  I made a change
> to eth_miim.v that fixes this problem and makes BUSY turn on
immediately.
> 
> Original:
> assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy |
> InProgress | InProgress_q3 | Nvalid;
> 
> Modified: (added WCtrlData and RStat)
> assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart |
> SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
> 
> Is this the correct fix? or is the observed behaviour expected?
> 
> Dennis Scott
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