RE: [ethmac] WishBone bug?

[e96ta@NOSPAM_efd.lth.se]

Well, that's ok... but you _might_ want to document this, clearly and visible in large red letters... :-) We assumed WISHBONE compliance, and 2 cycle transfers are NOT requiered in the spec. Oh well. We tried delaying our transfers to 2 cycles, and it indeed works alot better.

Will the burst-transfer work in the same way? I.e each and every transfer lasts (at least) 2 cycles, OR will ACK every cycle work, after the burst has been initialized?

(We have an external (to the eth) SDRAM-memory controller with custom managed cachebuffers, to try to hide the huge sdram latency and benefit from practically free burst-rates. Thus we have (at most times) data available, stable and ready.)

/Torbjörn and Mathias

----- Original Message ----- 
From: "Igor Mohor" <igorm@o... > 
To: <ethmac@o... > 
Date: Fri, 4 Oct 2002 08:55:16 +0200 
Subject: RE: [ethmac] WishBone bug? 

> 
> 
> Hi, Torbjörn and Mathias. 
> 
> Ok, I see know what's wrong. The memory controller or whatever is 
> connected 
> on the other side of the Ethernet WISHBONE master interface 
> generates 
> acknowledge signal m_wb_ack_i. An assumption has been made that 
> acknowledge 
> signal is delayed at least one clock signal (that's the minimum 
> when ack 
> signal 
> is registered). 
> 
> Best regards, 
> 	Igor
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