RE: [ethmac] ethmac project

[xande@dcc.ufmg.br]

  Hi, I'm here again.
  I'm using Xilinx ISE 4.2i. I switch on the option Synthesize -> FPGA 
Express Synthesis Options -> Enable Verilog Preprocessor. But the errors 
remains. The error message is:

Attempting to create d:\eth3\ethernet\__express_prj
Creating Project d:\eth3\ethernet\__express_prj\eth_defines
Creating library unisim
C:\Xilinx\vhdl\src\unisims\unisim_vcomp.vhd added to library in Express 
project
Analyzing C:\Xilinx\vhdl\src\unisims\unisim_vcomp.vhd ...
Adding d:\eth3\ethernet\rtl\verilog\eth_defines.v to Express project
Analyzing d:\eth3\ethernet\rtl\verilog\eth_defines.v ...
Analyzing C:\Xilinx\vhdl\src\unisims\unisim_vcomp.vhd ...
Analyzing d:\eth3\ethernet\rtl\verilog\eth_defines.v ...
<IMPLEMENT> Can't get design for top module/entity eth_defines
Done: failed with exit code: 0001.

   Somebody help me please.

----- Original Message ----- 
From: "Igor Mohor" <igorm@o... > 
To: <ethmac@o... > 
Date: Tue, 1 Oct 2002 15:46:56 +0200 
Subject: RE: [ethmac] ethmac project 

> You must have support for 'ifdef switched on. 
> 
> Regards, 
> 	Igor 
> 
> > -----Original Message----- 
> > From: owner-ethmac@o...  
> [mailto:owner-ethmac@o... ]On 
> > Behalf Of xande@d...  
> > Sent: 1. oktober 2002 12:04 
> > To: ethmac@o...  
> > Subject: [ethmac] ethmac project 
> > 
> > 
> >    Hi. I´m a newbie in this forum. 
> >    I´m interested in the ethmac project but I don´t succeed in 
> the 
> > compiling the sources (.v) 
> >    I´m use the Xilinx but error are generated. 
> >    Anybody knows can I do to compiling? 
> >    Somebody has the npl project? 
> >    I´m using the ethernet.tar.gz that I get in the 
> > http://www.opencores.org/projects/ethmac/ 
> >    Thanks. 
--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml