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RE: [ethmac] fifo reset
27-Feb-02
yxzhou Hi,
Not sure
what altera-wizard/xilinx-core-gen provide as I myself only use them for "pure"
memorey/pll module but why not build a rewind fifo yourself
?
the
basic concept is to have two set of couters let say radd (read address) and
radd_mark (read address mark)
at
start both are 0
as you
read the radd is incremented.
at the
end of the packet you move the radd_mark to the radd
position.
so far
nothing intresting
now
let say radd=50 and radd_mark=50 and another packet is
trasmited
and
let say when radd=60 you get a collision
all
you do is load the radd with the radd_mark and Walla you get a rewind
fifo.
keep
in mind that for full signal (in the write side) you MUST use the radd_mark as
otherwise you might over run the data and can't later re-trasmite
it.
have a
nice day
Illan
Hi,
In my design ,Fifo is used to store
the frame data that is to be transmitted.When col occurs during
transfer,
the frame will be
re-transmitted.I want to reset the read point(read address) only when col
occurs.Then it is not
neccessary to
transfer data from memory to fifo.But i can not find any core in xilinx that
provides the function to
reset read
point.Who can give me a suggestion on how to reset the read point? Or any
better methods ?
Thanks.
yxzhou