Re: [ethmac] reg-testbench module

Hi Igor,

sorry for late reply since I am out of station.I checked for whatever you mentioned and everything is correct.what I am looking for is,say suppose I have some data on wb_dat_i and I want it to be transported on Mtxd line.But here that lince is just showing 0.I couldnt understand,pls help me.

awaiting for ur reply.

thanks and regards

- satya

The correct wishbone cycle should have:

- wb_cyc set to 1

- wb_stb set to 1

- wb_adr valid

- wb_wr set to 1 for write or o for read cycle

- in case of read cycle data is latched to wb_dat_o when wb_ack is active.

In other words if there are wb_cyc and wb_stb activated but wb_adr is xxx then this is a bug.

In case of write cycle wb_dat_i must be valid, wb_dat_o can be xxx. I'm talking for slave interface.

In case of read cycle wb_dat_o must be valid when wb_ack_o is activated, wb_dat_i can be xxx.

I'm talking again for slave interface.

Do you have problems with that?

Are you seeing xxx values when setting the eth mac registers or buffer descriptors?

Regards,

Igor

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of satya
Sent: 11. februar 2002 6:20
To: ethmac@opencores.org
Subject: Re: [ethmac] reg-testbench module

Hi Igor,

when I try to simulate the core,the core is perfectly working on PHY side but I m facing problems on Hoster Interface side.I am not using wishbone dam interface.so I commented the statement in defines file.But the data to the wishbone is being fed like this:

once clock cycle some data and next xxxx and data and xxxx. I dont understand y u r doing like this.Please elaborate it if u dont mind.Awaiting for ur reply.

Thanks and regards

- satya

----- Original Message -----

From: Igor Mohor

To: ethmac@opencores.org

Sent: Saturday, February 09, 2002 4:01 PM

Subject: RE: [ethmac] reg-testbench module

What do you mean by not working properly? What errors do you get. I simulate with those files every day and it works

perfectly.

I would say that by not working you mean that there are no waves to see on the screen. I know that.

Open a wave wave window by yourself and then run the simulation after it's finished add signals to the wave window.

Do this sequence to do that:

First run the simulation and then type this (or add to the top_modelsim.do file)

view wave

add wave -r /*

restart -f

run -all

Regards,

Igor

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of satya
Sent: 9. februar 2002 6:48
To: ethmac@opencores.org
Subject: [ethmac] reg-testbench module

Hi Igor,

the bench file you have given is not working properly when I try to simulate in Modelsim.Can you please help me in this regard?

awaiting for your reply.

Thanks and Regards

- satya