RE: [ethmac] Non-DMA Host Interface

Hi, Donna.

I expect it to be finish at the beginning of the new year. The buffer descriptor will contain also the pointer to the memory where the frame is stored. For that reason the wishbone master interface will be added. I didn't draw any diagrams by myself, more use them for some other documentation.

I would really love if you would keep me updated with your progress.

Regards,

Igor

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of Donna Nyman
Sent: 27. december 2001 18:36
To: ethmac@opencores.org
Subject: [ethmac] Non-DMA Host Interface

Hi Igor,

Can you tell me when the host interface that doesn't use DMA will be completed? Do you have any preliminary information on it? We are planning to implement the ethernet core into our ASIC, and the non-DMA interface will work much better for us. We will be implementing an FPGA version in about six weeks and then the ASIC after that.

Also, do you have any timing diagrams that could be added to the ethernet core documentation? That would be very helpful!

Thanks!

Donna

-----Original Message-----
From: Igor Mohor [mailto:igorm@opencores.org]
Sent: Thursday, December 27, 2001 3:19 AM
To: ethmac@opencores.org
Subject: RE: [ethmac] pls clarify my doubts

Hi,

1. The source address is built from 48 bits like: 01-02-03-04-05-06. You can get the first 24 bits from the ieee organisation. The other 24 bits are up to you. You can use serial number of the board or something like that.

2. It is up to the host to set the destination address and not up to MAC. From the MAC's point of view the destination address is just part of the packet to send. Host can use anything for the destination address.

3. Yes. And that source must add the destination and source address to the data. I'm writing a host interface that won't use DMA but normal wishbone cycles to get/store the data.

Regards,

Igor