[ethmac] Status

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

Yes.
One is MAC Control module, another one is host (wishbone) interface to the
OR1k.
I'm working on the control module now. Everything is clear about it. I have
more
concerns about the host interface to the Or1k processor. Things like packet
status,
dma access, address recognition, etc. need to be defined. Any suggestions?
Perhaps somebody has something done already.

The Tx and the Rx modules are by the ethernet spec. avaliable from the
opencores
webpage. I just changed few minor things and have to update the document.
I'll do that
during the weekend.

Regards,
	Igor

> -----Original Message-----
> From: 97024 Hendra Gunawan [mailto:hendrag01@students.ee.itb.ac.id]
> Sent: 28. junij 2001 5:48
> To: Igor Mohor (uni-mb)
> Subject: Re: [ethmac]
>
>
>
>
> hi'
>
> is there any modules have not completed yet?
>
>
>

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