[ethmac] Status of Open Ethernet MAC Core / Eventual Contribution

[97024 Hendra Gunawan <hendrag01@students.ee.itb.ac.id>]

hi'

i just exchange lines 88 & 89 with 91 & 92 of FCS_checker.v, because a
delay happened to signal FCS_start_check, so i think the
initialization of FCS_start_check better be done first and the sequence
should be changed.
 
but i tried to simulate again the Rx module many times, it works without a
change. so, i think the first source codes are right. i don't know why
when the first time i simulated it, it didn't work.

i take a conclusion that the original Rx codes are right. nothing's wrong.

i'm interested too to try implementing the Ethernet core into FPGA. may i
know what type of FPGA will you use?

thank for your attention

best regards

Hendra