RE: [ethmac] BFM model for MII_RX i/f

["Illan Glasner" <iglasner@zumanetworks.com>]

23-Dec-00
 
   All Hi,
 
        Once the code is always importent I think first thing should be
to send or at least in parallel to the code an explanation of what the
code so , meaning state-machine drawing timing diagram block diagram etc
etc.
 
simple the papers you used to design what you have.
 
The point is that while the code is importent as we can look and see if
there is no bugs etc as well as verify the correction the first thing in
my opinion is to see that the concept is right and only than "waste"
time on verifying the code.
 
more over while some use vhdl other used verilog but diagram can be
verify by all.
 
the code itself while can be written very smart or just brut-force is
less crusial.
 
so for exmaple in mii core, maybe a better thing would be first to
discuss what we want it to do, for example just read the phy ?
how many phy to support ?
which reg to support ?
maybe to support also auto-neg ?
or maybe we only care about the link status ?
etc etc
 
than once we decide what this code need to do, , than we can talk about
how to do , which frequancy we shall support, duty-cycle maybe as well ,
and than we can go to the implemintation which is just pure "black-work"
as once all is define anyone can do it's own writing , this is the
"simple" part.
 
just my opinion
 
have a nice day
 
   Illan

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
Behalf Of Kostas Pramataris
Sent: Thursday, November 30, 2000 6:22 AM
To: ethmac@opencores.org
Cc: maik@opencores.org
Subject: [ethmac] BFM model for MII_RX i/f



Hi all

I've written a bus functional model for the MII receive i/f. The model
reads packet-data from a file and drives them to the MII RX i/f. The
model could be used for building a testbench for the ethmac_receiver.

Attached is the vhdl file for the model, a required package and a sample
packet-file.

regards,

kostas

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