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[cvs-checkins] camera/rtl/verilog camera_y_table.v camera_tpr ...

CVSROOT:	/home/oc/cvs
Module name:	camera
Changes by:	tadejm	03/07/14 17:59:02

Modified files:
	rtl/verilog    : camera_y_table.v camera_tpram.v 
	                 camera_sync_ctrl.v camera_defines.v 

Log message:
	BLOCK RAM changed for case. BIST inserted for Virtualsilicon 64x32 ram

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