[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...

CVSROOT:	/home/oc/cvs
Module name:	mem_if
Changes by:	mihad	02/12/13 20:04:07

Modified files:
	bench/verilog  : mem_if_bench.v mem_if_sdram_flash_sim_top.v 
	doc            : README.txt 
	sim/rtl_sim/bin: rtl_file_list 
Added files:
	bench/verilog  : mem_if_bench_defines.v 
	rtl/verilog    : mem_if_registered_feedback.v mem_if_ro_top.v 

Log message:
	Added files for registered feedback.
	Added file for testbench definitions.
	doc and bench directories are currently not really up to date.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml