[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] pci/rtl/verilog pci_bridge32.v pci_target_unit ...

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	tadejm	02/10/18 02:36:41

Modified files:
	rtl/verilog    : pci_bridge32.v pci_target_unit.v pci_tpram.v 
	                 pciw_pcir_fifos.v top.v wb_slave_unit.v 
	                 wb_tpram.v wbw_wbr_fifos.v 

Log message:
	Changed wrong signal name scanb_sen into scanb_en.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml