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[cvs-checkins] ethernet/rtl/verilog eth_wishbone.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_wishbone.v
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Fri, 11 Oct 2002 14:35:37 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/10/11 14:35:30

Modified files:
	rtl/verilog    : eth_wishbone.v 

Log message:
	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
	TxDone and TxRetry are generated after the current WISHBONE access is
	finished.

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