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[cvs-checkins] ata/rtl/vhdl/ocidec3 ro_cnt.vhd ud_cnt.vhd

CVSROOT:	/home/oc/cvs
Module name:	ata
Changes by:	rherveille	02/03/01 04:49:26

Added files:
	rtl/vhdl/ocidec3: ro_cnt.vhd ud_cnt.vhd 

Log message:
	Changed internal counter libraries.
	Split counter.vhd into separate files.
	Core is in same state as Verilog version now.

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