[cvs-checkins] uart16550/ tl/verilog/uart_receiver.v tl/veril ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/12/06 15:51:10

Modified files:
	rtl/verilog    : uart_receiver.v uart_regs.v uart_top.v 
	                 uart_wb.v 
	sim/rtl_sim/bin: nc.scr 

Log message:
	Bug in LSR[0] is fixed.
	All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.

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