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[cvs-checkins] or1k/mp3/rtl/verilog/or1200 alu.v cpu.v define ...

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	01/11/12 02:45:51

Modified files:
	mp3/rtl/verilog/or1200: alu.v cpu.v defines.v id.v 
	                        operandmuxes.v rf.v sprs.v 

Log message:
	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.

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