Re: [oc] Registers - Multi clock domains

[Gunnar Dahlgren <gunnar.dahlgren@axis.com>]

At 11:00 2003-07-31 +0100, yakgna narayanan wrote:
>hi,
>I am having one technical doubt, can anyone clear this
>My doubt is :
>
> how to handle register for multi clock domains ?
> say for e.g
> rega      - 8 bit register
> write clk - clk1
> read clk  - clk2
> For data transfer means we can go for Asynchronous
> fifo, whereas for registers, individual bit setting
> and clearing is done in different clocks, so we cant
> go for RAM's also. So please guide me how to do
> verilog code for registers in multi clock domains.
>

OK, as I understand it you basically want a 1-bit register
(flip-flop) that you can set from one clock domain and
clear from another? (this case would then easily be
generalised to a multi-bit register) Then it all comes down
to the classic synchronisation-of-asynchronous-signals
problem.

Say that you have a set signal in clk1 domain and a clear
signal in clk2 domain.

One basic solution would be to keep the register in e.g.
the clk1 domain and synchronise the clk2 signal to clk1
before using it as a clear signal:

reg    rega;     // a one-bit register
reg    set_sig;  // your clk1 set signal
reg    clr_sig;  // your clk2 clear signal
reg    clr_s1;
reg    clr_sync; // clear signal synchronised to clk1

... (code that produces set_sig and clr_sig) ...

always @ ( posedge clk1 ) begin
  // Syncronisation of clr_sig
  clr_s1 <= clr_sig;
  clr_sync <= clr_s1;
  // The S/R register
  // (gives set priority over clr)
  if( set_sig ) begin
    rega <= 1;
  end else if( clr_sync ) begin
    rega <= 0;
  end
end

For this to work, the frequency of clk2 must be strictly
smaller than the frequency of clk1 (alternatively, the
clr_sig must only change its value every other clk2 cycle
or something, the bottom line is that clr_sig always has
to be constant for more than one clk1 cycle at a time -
and for the same reason clr_sig should come directly from
a clk2-clocked FF, not from some general combinatorial
clk2 logic).

As you see, the clr_sig is synchronised through two flip-
flops. You need two since the first may sample the clr_sig
signal in the middle of a transition. In this case the
first FF may become metastable and output a voltage level
somewhere between the 0 and 1 levels. When that happens,
the probability that the FF falls back into either the 1
or the 0 state grows exponentially with time. The second
FF samples the first after one entire clock period, after
that long time you can usually be "almost sure" that the
metastability is gone (but not quite, you never can be as
far as I know... But when you get down to something like 1
error in 10 or 100 years it's quite negligible for most
applications).

One problem here is that the metastability-fallback-
probability exponential function seldomly is presented
by the process vendor. As long as you're not too close to
the process frequency limits or as long as a metastability
failure is not life-threatening, you can probably live
happily and safely with the two-flip-flop approach.

I hope this solved your problem.

Best regards
Gunnar Dahlgren
ASIC designer @ Axis Communications AB, Sweden

>
> Thanks in Advance,
> Regards,
> Yakgna
>
>
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