Re: [oc] x86 IP Core

[antti@case2000.com]

bochs is open source 386 + PC hardware emulater in C++
it would be possible to compile it for some softcore in ASIC
it is possible to use some hardcore MCU (like in V2Pro) or full
soft core, but sure it would be one softcore emulating another
so speed would drop, OTOH it may make sense to develop
a specialized core (not x86) that can emulate x86 relativly fast
somewhat similar approuch as MemoryLogix or Transmeta

x86 Core options:

1) cycle accurate clone (real headache)
2) classical microcode engine (boring)
3) microcode engine that can reload on the fly - you could achieve
even full pentium 6 support because new microcodes are loadable
(well speed penalty)
4) custom VLIW machine emulating x86
5) some C programmable RISC emulating x86 - this is free option. 
but I looked at bochs, trying to compile them for fpga core, I would 
rather write an emulator in pure assembler, if I have time I could
try to compile bochs with GCC-MB or GCC-PPC but I guess it will
be a disaster :(
6) x86 Kernel-1 approuch - a x86 core that has minimal functionality to 
be an x86 emulator, it has some instructions implemented, all non 
implemented will fall through below highest 386 kenrel ring, Kernel(-1) 
/is now my definition/, in Kernel(-1) mode all the instruction the core 
does not support are emulated. This is faster than emulating with non 
x86 based machine. Again this approuch also allows full pentium support 
(speed penalty applies). And it allows the configurable core, for either 
speed or size. In all configurations Pentium class instruction could be 
supported.

***
clarification, you can not get 386 and no v8086, virtual 8086
mode is built in, supporting it makes the 386 core much larger
(that is what legacy means)

and another clarification Easypath is not FPGA ie it is mask version
of FPGA, well ok you could say same thing. I think xilinx calls it
"EASY PATH" to ASIC
but you can get ASICs in IBM blue (0.7micron copper) that include
Xilinx FPGA fabric as macrocells, so the ASIC/FPGA boundaries
are floating a bit.

antti

 



----- Original Message ----- 
From: Rudolf "Usselmann (OpenCores)" <rudi@o... > 
To: cores@o...  
Date: 28 Jul 2003 22:56:36 +0700 
Subject: Re: [oc] x86 IP Core 

> 
> 
> On Mon, 2003-07-28 at 23:17, antti@c...  wrote: 
> > From: Rudolf "Usselmann (OpenCores)" <rudi@o... > 
> > > 
> > > Anybody know of a free or really cheap x86 IP core ? 
> > > 286 or 386 would do fine. 
> > 
> > what is the target technology? 
> > how fast it needs to be? 
> > how small it should be? 
> 
> I'm looking for a Soft IP core so the above will 
> depend on my technology. Size is always as small 
> as possible. 
> 
> > should it support v8086 mode or could be only 386 protected 
> mode? 
> 
> Well, I really only need 386, but will take what I 
> can get. I can always modify it. 
> 
> > you could compile bochs for V2Pro, getting possible some MIPS 
> 
> What is "bochs" ? 
> 
> > out of it in 386 mode, but cheapeast V2Pro's are 30$ in huge 
> > quantity, (xilinx dreams?). 
> > they promise 80% reduction for Easypath devices, 
> > but smallest applicable is VP30 
> > that costs hm I dont know, VP20 is 600$ one off, 
> > VP30 850?, one off price 
> > 270, qty 100k?? 
> > 80% off 54$ ? wild guesses. 
> > 
> > but I am afraid you need low power core :) 
> 
> My final application will NOT be FPGA. 
> 
> > antti 
> 
> Regards, 
> rudi 
> -------------------------------------------------------- 
> www.asics.ws  --- Solutions for your ASIC/FPGA needs --- 
> ----------------- FPGAs * Full Custom ICs * IP Cores --- 
> FREE IP Cores --> http://www.asics.ws/ <-- FREE IP Cores 
> 
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml