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RE: [oc] synthesis error

Hi,
That error usually occurs when a signal (ready in this case) is driven by
multiple inputs.
Hope this helps. Good luck!
Rita

-----Original Message-----
From: spyros [mailto:spyros_s@freemail.gr] 
Sent: quinta-feira, 10 de Julho de 2003 14:34
To: cores@opencores.org
Subject: [oc] synthesis error

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

hi all,
i'm trying to synthesize a project with leonardo,
  but i get the following error:

ERROR: a power net is driven by primitive gate(s) --  NET: ready

can someone explain to me what is this supposed to mean?
I googled and searched leonardo's manuals but till now nothing.

TIA,
spyros

- --

φοιτητής στο Δ.Π.Θ

student @ DUTH

public key: dalab.ee.duth.gr/~spyros/my_pub.asc


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