Re: [oc] CAN core in VHDL

[=?gb2312?q?jean=20pop?= <popjeandu@yahoo.com.cn>]

Dear Sir:
  wIould like to know ananlysis the VHDL Code So i request your to
send
me a Free Ip Core
          Thanking you
                        with regards

 

                 POPJEANDU@YAHOO.COM.CN

 

 

kamal_eee@rediff.com wrote:

Sir
i would like to know ananlysis the VHDL Code So i request your to send me a Free Ip Core
Thanking you
] with regards
D.Kamal
----- Original Message -----
From: bob@d...
To: sobanc@n... , cores@o...
Date: Tue, 8 Jul 2003 23:17:51 -0100
Subject: Re: [oc] CAN core in VHDL

>
>
> Hello,
>
> I am planning to use the VHDL CAN core. Is there any status to
> report
> on verification of the VHDL model? Are there any known bugs or
> fixes to
> the code available on the web site?
>
> thanks,
> bob
>
> ----- Original Message -----
> From: Soban Shoeb Chawre
> To: cores@o...
> Date: Mon, 24 Mar 2003 12:20:45 +0530
> Subject: Re: [oc] CAN core in VHDL
>
> >
> >
> > hello,
> >
> > I am interesred in verifying the core.
> >
> > plz send the core, i have modelsim full version.
> >
> > thank you.
> > > Shehryar Shaheen wrote:
> > >
> > > Hello,
> > > I have translated Igor Mohr's CAN Core in VHDL.
> > >
> > > But it has to be tested and verified (and debugged!). If
> any
> > body has
> > > full
> > > version of ModelSim (or any other simulator that
> > > supports mixed HDL simulation) and is interested in
> verifying
> > the core
> > > then
> > > I can send hime the core and it can be verified using the
> > Verilog
> > > testbench
> > > with orignal Verilog core.
> > >
> > > Here a link that shows how to do mixed HDL simulations in
> > ModelSim
> > > (It's pretty simple!)
> > >
> >
> http://jason.sdsu.edu/modelsim/se_html/tutorial_html/t_mixed.shtml
> > >
> > > Anybody interested in doing this let me know
> > >
> > > Regards
> > >
> > > Shehryar
> > >
> >
>
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