Re: [oc] Clock frequency generator

[Vikrant Shinde <vikrantps@yahoo.com>]

Thank you Mohamed and Jim Dempsey for your replies.
Mohamed with regards to your questions...my source is
synch/asynch data and target a FPGA which will get the
data and clk. The clk is to be generated from an
on-board oscillator. 
Similar to what Jim explained in his
suggestions...something additional you can think of is
always welcome.

Regards,
Victor. 
--- Mohamed Soliman <mohamedsoliman235@yahoo.com>
wrote:
> I did not understand your target, what do you meen
> by matching it with the system clock or comparing it
> with system clock ? unother question is that what is
> the sensitivity list of the process that generat
> this clock ? I hope we can more helpful if you
> explain that.
> Regards
> 
> cool_canguy@indiatimes.com wrote:
> hello,
> 
> i am looking to match the system clock with a square
> wave in VHDL. so 
> in my code for SQ wave...if I am generating wave as
> below
> 
> counter := counter + 1;
> 
> if counter = 40 then
> sqwave_out <= '1';
> end if;
> 
> if counter = 80 then
> sqwave_out <= '0';
> counter := 0;
> end if;
> 
> where sqwave_out is the sq. wave then how can I
> match the system 
> clk with this wave. ie compare both...can someone
> demonstrate this to 
> me in VHDL code? 
> 
> many thanks,
> Victor
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