[oc] Problem in DMA IP Core Trace ?

[NansonHuang@itri.org.tw]

 Hi,

  Now I am tracing the DMA IP Core. In the wb_dma_pri_enc_sub.v, it firstly
defines the parameter pri_sel to 2'h0. Then it is used in "Select
Configured Priority" mux.
However, it's value is 2'h0 always. Could someone explain the mux is
necessary ? Synthesis tools will optimize it to dedicated value 2'd0:
pri_out_d = pri_out_d0. Am I right ? How to explain the code ?

 Appreciate for any info.

 Nanson

== Code Segment ===

`include "wb_dma_defines.v"

// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration

module wb_dma_pri_enc_sub(valid, pri_in, pri_out);

parameter [3:0]   ch_conf = 4'b0000;
parameter [1:0]   pri_sel = 2'd0;

input       valid;
input [2:0] pri_in;
output      [7:0] pri_out;

wire  [7:0] pri_out;
reg   [7:0] pri_out_d;
reg   [7:0] pri_out_d0;
reg   [7:0] pri_out_d1;
reg   [7:0] pri_out_d2;

assign pri_out = ch_conf[0] ? pri_out_d : 8'h0;

// Select Configured Priority
always @(pri_sel or pri_out_d0 or pri_out_d1 or  pri_out_d2)
      case(pri_sel)           // synopsys parallel_case full_case
         2'd0: pri_out_d = pri_out_d0;
         2'd1: pri_out_d = pri_out_d1;
         2'd2: pri_out_d = pri_out_d2;
      endcase


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