Re: [oc] I2C noise filtering

[Richard Herveille <richard@asics.ws>]

IMHO an expensive suggestion.
Is this a Xilinx topic?? I know Altera doesn't really care wether you put scl 
on a GPIO or a dedicated clock pin. It automatically reroutes the signal to 
the dedicated hi-speed clock lines in the device. Timing might be affected 
though; caused by the additional delay, and the rerouting uncertainty (added 
clock jitter).

Richard

>    Hi,
>
>          Or use two pin the Gclk for input and a general IO to streach and
> connect both to the external SCL line thus "enjoying from both world"
> meaning easier routing as well as capable to streach the clock.
>
> Of course you "pay" for this in extra pin but I would assume in most cases
> you have this extra pin and the gain might even allow you to use smaller
> device.
>
> have a nice day
>
>    Illan
>
> -----Original Message-----
> From: Richard Herveille [mailto:richard@asics.ws]
> Sent: Monday, November 25, 2002 10:50 AM
> To: cores@opencores.org
> Subject: Re: [oc] I2C noise filtering
>
>
>
> You are talking about the i2c slave again right??
> Both SCL and SDA are bidirectional signals (inout). So you probably do want
> to
> use general purpose IOs for SCL and SDA. Unless you do not support clock
> stretching (wait state generation), in that case you can use a global clock
> pin for the SCL line. Although I2C is so slow it shouldn't matter (might
> ease
> up routing in you FPGA though).
>
> > my clock is 10mhz (xilinx) and both sda and scl is tied to general IO.
> >  So, like you said,  I have to output po_scl_cln to another general IO
> > and and tie it to Global clk pin?  Is there any way to avoid it
> > because it's too difficult to solder such a small and close pin chip.
> >  And also, I thought start and stop condition will reset all, but why
> > there is another reset for it?  Since I don't have choice for reset on
> > the board, will that be an issue?
> >
> >
> >
> > Ken
> >
> > ----- Original Message -----
> > From: Illan Glasner <IGlasner@m... >
> > To: "'cores@o... '" <cores@o... >
> > Date: Wed, 6 Nov 2002 19:14:54 -0800
> > Subject: RE: [oc] I2C noise filtering
> >
> > > Hi,
> > >
> > >    You can try something like :
> > >
> > > reg     [2:0]   scnt;
> > > always @(posedge pi_clk or negedge rstn)
> > > if (~rstn)
> > >    scnt <= #1 0;
> > > else if (scl)
> > >    scnt <= #1 (scnt==7) ? 7 : scnt + 1 ;
> > > else
> > >    scnt <= #1 (scnt==0) ? 0 : scnt - 1 ;
> > >
> > > reg     po_scl_cln   ;
> > > always @(posedge pi_clk)
> > > if (~rstn)
> > >    po_scl_cln <= #1 0;
> > > else
> > >    po_scl_cln <= #1 scnt[2] ;
> > >
> > >
> > > keep in mind that if you use Xilinx you probably will need to send
> > > po_scl_cln to a general IO make an external connection on the board
> > > to GCLK
> > > IO in order to use the clock resource.
> > >
> > > if you are using altera in this matter it should be easier as you
> > > can use
> > > directly the po_scl_cln.
> > >
> > > where pi_clk is a high frequncy clock much faster than the scl
> > > something
> > > like 10M.
> > >
> > > if you don;t have high frequnacy you can make another "loop" of
> > > geenral IO
> > > to GCLK input and simple generate internaly a free runing ring osc
> > > using let
> > > say 6 buffer and invertor and this should do the job.
> > >
> > > have a nice day
> > >
> > >    Illan
> > >
> > >
> > >
> > > -----Original Message-----
> > > From: ckh827@h...  [mailto:ckh827@h... ]
> > > Sent: Wednesday, November 06, 2002 8:01 PM
> > > To: cores@o...
> > > Subject: [oc] I2C noise filtering
> > >
> > >
> > >
> > >
> > > When I try to synthesize the I2C verilog from Richard (Opencores),
> > > It
> > > said unable to open timescale.v. But I already added the source in
> > > the
> > > project.  Anybody has any idea?
> > >
> > > And also, how can I filter out the noise from scl and sda lines?
> > >
> > > I'm urgently need a working I2C slave model because I already
> > > worked
> > > for more than 3 weeks but still not able to ping correctly.
> > >
> > > Any help is appreciated.
> > >
> > > Ken

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