[oc] CFFT TestBanch for Saumil

[sradio@opencores.org]

This test banch is writen by Saumil, I only add some signals to explain
the output order.
For simulation, you need checkout the new version of CFFT.
If it work well, let me know. I will add it to the project.


library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.std_logic_unsigned.all;
use std.textio.all;
use IEEE.std_logic_textio.all;

entity tb_cfft1024x12 is

end tb_cfft1024x12;

architecture tb of tb_cfft1024x12 is

component cfft1024X12
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 inv : in std_logic;
                 Iin : in STD_LOGIC_VECTOR(11 downto 0);
                 Qin : in STD_LOGIC_VECTOR(11 downto 0);
                 inputbusy : out STD_LOGIC;
                 outdataen : out STD_LOGIC;
                 Iout : out STD_LOGIC_VECTOR(13 downto 0);
                 Qout : out STD_LOGIC_VECTOR(13 downto 0);
		 		 OutPosition : out 
STD_LOGIC_VECTOR( 9 downto 0 )
             );
end component;

signal  clk : STD_LOGIC;
signal  rst : STD_LOGIC;
signal  start : STD_LOGIC;
signal  inv : std_logic;
signal  Iin : STD_LOGIC_VECTOR(11 downto 0);
signal Qin : STD_LOGIC_VECTOR(11 downto 0);
signal inputbusy : STD_LOGIC;
signal outdataen : STD_LOGIC;
signal Iout : STD_LOGIC_VECTOR(13 downto 0);
signal Qout : STD_LOGIC_VECTOR(13 downto 0);
signal Io : STD_LOGIC_VECTOR(13 downto 0);
signal Qo : STD_LOGIC_VECTOR(13 downto 0);
signal output_position:std_logic_vector(9 downto 0 );
signal OutPosition:std_logic_vector(9 downto 0 );


begin
f: cfft1024x12 port map(clk=>clk,
                        rst =>rst,
                        start=> start,
                        inv=>inv,
                        Iin=>Iin,
                        Qin=>Qin,
                        inputbusy=>inputbusy,
                        outdataen=>outdataen,
                        Iout=>Iout,
                        Qout=>Qout,
					
	OutPosition=>OutPosition
						);
-- to adjust the output sequence
--Io(0)<=Iout(12);
--Io(1)<=Iout(13);
--Io(2)<=Iout(10);
--Io(3)<=Iout(11);
--Io(4)<=Iout(8);
--Io(5)<=Iout(9);
--Io(6)<=Iout(6);
--Io(7)<=Iout(7);
--Io(8)<=Iout(4);
--Io(9)<=Iout(5);
--Io(10)<=Iout(2);
--Io(11)<=Iout(3);
--Io(12)<=Iout(0);
--Io(13)<=Iout(1);
--
--Qo(0)<=Qout(12);
--Qo(1)<=Qout(13);
--Qo(2)<=Qout(10);
--Qo(3)<=Qout(11);
--Qo(4)<=Qout(8);
--Qo(5)<=Qout(9);
--Qo(6)<=Qout(6);
--Qo(7)<=Qout(7);
--Qo(8)<=Qout(4);
--Qo(9)<=Qout(5);
--Qo(10)<=Qout(2);
--Qo(11)<=Qout(3);
--Qo(12)<=Qout(0);
--Qo(13)<=Qout(1);
output_order:process(clk)
variable counter:std_logic_vector( 9 downto 0 ):="0000000000";
begin
     if clk'event and clk='1' then
            if outdataen='1' then
                   counter:=counter+1;
            end if;
			output_position<=counter( 1 downto 0 )&
                                       counter( 3 downto 2 )&
                                       counter( 5 downto 4 )&
                                       counter( 7 downto 6 )&
                                       counter( 9 downto 8 );

     end if;
end process output_order;


clockgen: process
begin
        clk <= '1';
        wait for 5 ns;
        clk <= '0';
        wait for 5 ns;
end process;

process
file FileIn1 : text is in  "bindata"; -- bindata file contains 1 to 1024 in
	binary
variable LineIn1   : line;
variable InputTmp1 :std_logic_vector(11 downto 0);
variable feed   : integer:=1;
begin
        if feed=1 then
                rst<='1';
                wait until clk'EVENT and clk='1';
                rst<='0';
                wait until clk'EVENT and clk='1';
                inv<='0';
                start<='1';
                wait until clk'EVENT and clk='1';
                start<='0';
                Qin<="000000000000";
                while  not( endfile( FileIn1)) loop
                        readline( FileIn1, LineIn1);
                        read(LineIn1, InputTmp1);
                        Iin<=InputTmp1;
                        wait until clk'EVENT and clk='1';
                end loop;
                feed:=0;
        end if;
end process;

end tb;


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