Re: [oc] about instance components

[haoguang.guo@philips.com]

 Thank you for your response! i used the xilinx ise and verilog xst as synthisis.
 I write a module and want to cascade the module by n times. but i fail to find a easy way to
impelement it like vhdl.please help me!
thank you !







On Mon, Nov 18, 2002 at 07:08:44PM -0800, haoguang.guo@philips.com wrote:
> hi,
>    i am a newbie for verilog hdl. I have a problem to instance N times of same components in xilinx ise4.1.
> Here N is a paremeter.It seems the verilog does not support GENERATE like VHDL.
>   please help me !
> thank you
>
newer verilogs (2001 standard compliant at least) support the
generate statement

what verilog simulator/synthesis are you using?

John
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