RE: [oc] I2C noise filtering

[Illan Glasner <IGlasner@mrv.com>]

   Hi,

	you technicly can drive FF from another FF however this mean that
you don;t go through the global clock routing.

the small thing is that you simple waste routing for other thing you might
want to do.

the big thing is that you might have to do hand placment to help to tool as
not using the global clock routing mean that there is no more fix clock sqew
between FF and thus gurenty that they will work properly.

just assume you have a two stage shift register and the first get the clock
at time t+1 while the second get the clock at time t+3 .

now assume that the clock to ouot plus routing delay from the first FF to
the second is only 1 

as a result you no more have shift register as both sample the same
information ont the same clock.

so it all fall to how much logic you have , how much the tool will be able
to meet timing which depend on routing resource and placment and lastly
maybe some work from you in the floorplaner.

not having external reset is "not nice" but many time you can ignore it as
usualy both altera and xilinx will come up with the FF in value 0 so if you
can "live with it" and set your code accordingly than no problem.

one small trick you might want to use is that if you a DLL you can use the
lock signal as your reset.

have a nice evening

   Illan

 

-----Original Message-----
From: ckh827@hotmail.com [mailto:ckh827@hotmail.com]
Sent: Wednesday, November 06, 2002 10:16 PM
To: cores@opencores.org
Subject: RE: [oc] I2C noise filtering


my clock is 10mhz (xilinx) and both sda and scl is tied to general IO.
 So, like you said,  I have to output po_scl_cln to another general IO
and and tie it to Global clk pin?  Is there any way to avoid it
because it's too difficult to solder such a small and close pin chip.
 And also, I thought start and stop condition will reset all, but why
there is another reset for it?  Since I don't have choice for reset on
the board, will that be an issue?



Ken

----- Original Message ----- 
From: Illan Glasner <IGlasner@m... > 
To: "'cores@o... '" <cores@o... > 
Date: Wed, 6 Nov 2002 19:14:54 -0800 
Subject: RE: [oc] I2C noise filtering 

> 
> 
> 
> Hi, 
> 
>    You can try something like : 
> 
> reg     [2:0]   scnt; 
> always @(posedge pi_clk or negedge rstn) 
> if (~rstn) 
>    scnt <= #1 0; 
> else if (scl) 
>    scnt <= #1 (scnt==7) ? 7 : scnt + 1 ; 
> else 
>    scnt <= #1 (scnt==0) ? 0 : scnt - 1 ; 
> 
> reg     po_scl_cln   ; 
> always @(posedge pi_clk) 
> if (~rstn) 
>    po_scl_cln <= #1 0; 
> else 
>    po_scl_cln <= #1 scnt[2] ; 
> 
> 
> keep in mind that if you use Xilinx you probably will need to send 
> po_scl_cln to a general IO make an external connection on the board 
> to GCLK 
> IO in order to use the clock resource. 
> 
> if you are using altera in this matter it should be easier as you 
> can use 
> directly the po_scl_cln. 
> 
> where pi_clk is a high frequncy clock much faster than the scl 
> something 
> like 10M. 
> 
> if you don;t have high frequnacy you can make another "loop" of 
> geenral IO 
> to GCLK input and simple generate internaly a free runing ring osc 
> using let 
> say 6 buffer and invertor and this should do the job. 
> 
> have a nice day 
> 
>    Illan 
> 
> 
> 
> -----Original Message----- 
> From: ckh827@h...  [mailto:ckh827@h... ] 
> Sent: Wednesday, November 06, 2002 8:01 PM 
> To: cores@o...  
> Subject: [oc] I2C noise filtering 
> 
> 
> 
> 
> When I try to synthesize the I2C verilog from Richard (Opencores), 
> It 
> said unable to open timescale.v. But I already added the source in 
> the 
> project.  Anybody has any idea? 
> 
> And also, how can I filter out the noise from scl and sda lines? 
> 
> I'm urgently need a working I2C slave model because I already 
> worked 
> for more than 3 weeks but still not able to ping correctly. 
> 
> Any help is appreciated. 
> 
> Ken 
> 
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