RE: [oc] FPGA constraint problem

[Illan Glasner <IGlasner@mrv.com>]

   Hi,

     General speaking you are correct however in many application there is
only one master for the scl and all the rest act as slave and in such case a
i2c-slave module can have the scl as input only (assuming also you don;t
need to do clock streaching).

have a nice day

   Illan

-----Original Message-----
From: Richard Herveille [mailto:richard@asics.ws]
Sent: Wednesday, October 30, 2002 11:20 PM
To: cores@opencores.org
Subject: Re: [oc] FPGA constraint problem



This is your I2C model right??
If you're really familiar with I2C (and you should), than you already know
the 
answer.

Both SDA and SCL lines are bi-directional.
Global clock lines are input only.
So can you tie SCL to a global clock line???


> I'm currently trying test my I2C .vhd project.  But, when I tried to do
> the contraints on my spartan2 fpga.  it gives me error that I have to use
> SCL as GCLKIOB.
>
> Do I really need to tie the SCL pin to one of the GCK?
>
> Can I contrains the SCL to any other port?

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