Re: [oc] New! FFT core

["hanzy" <zeyaohan@263.net>]

In your document: the line connect with cordic module and 4 point cfft I do not think is right. And I do not know whether the 4 point FFT read the pre stage's input and rotate factors from dual port ram, after do a radix calculation then output? and the selector selects one data from input data and rotate factors then decides write which one to dual port ram, the next 'step' put the other data to dual port ram?

I do not know whether you can figure out your fixed-point simulation result through a spectrum analyse, the better post simulation, and the fixed-point quantity error compared with Matlab result?

Can you give out the simulation or the real result from Spartan2e100 -6 and make a comparision with the exisit and good result?

And i still have not read your source code, when i am free i will read it.

B.R.



----- Original Message ----- 
From: <sradio@opencores.org>
To: <cores@opencores.org>
Sent: Thursday, October 31, 2002 8:55 PM
Subject: Re: [oc] New! FFT core


> 
> Welcome hanzy :)
> 
> This document is writen in two hours, so it was too simple,
> 
> give me some advice on what you are care about, I will write this part 
> first.
> 
> I write a fft sample with 1024 point 12 bit width, I put it at /cfft/imp
> 
> I try to fit it into Spartan2e100 -6, 
> The map result is:
> 
>    Number of Slices:                807 out of  1,200   67%
>    Number of Slices containing
>       unrelated logic:                0 out of    807    0%
>    Number of Slice Flip Flops:    1,174 out of  2,400   48%
>    Total Number 4 input LUTs:     1,294 out of  2,400   53%
>       Number used as LUTs:                      1,250
>       Number used as a route-thru:                 43
>       Number used as Shift registers:               1
>    Number of bonded IOBs:            57 out of    142   40%
>       IOB Flip Flops:                               1
>    Number of Block RAMs:              6 out of     10   60%
>    Number of GCLKs:                   1 out of      4   25%
>    Number of GCLKIOBs:                1 out of      4   25%
> Total equivalent gate count for design:  120,504
> Additional JTAG gate count for IOBs:  2,784
> 
> The post timing result is:
> Design statistics:
>    Minimum period:  10.580ns (Maximum frequency:  94.518MHz)
>    Minimum input arrival time before clock:   4.522ns
>    Minimum output required time after clock:   8.199ns
> 
> 
> ----- Original Message ----- 
> From: Rudolf Usselmann <rudi@a... > 
> To: cores@o...  
> Date: Thu, 31 Oct 2002 16:32:19 +0700 
> X-Virus: 1
> Subject: Re: [oc] New! FFT core 
> 
> > 
> > 
> > On Thursday 31 October 2002 15:27, hanzy wrote: 
> > > i just take a browse with your FFT core, i think your 
> > description is not 
> > > good, you can make more detailed description, and I will give 
> > you my 
> > > thoughts after careful read. 
> > 
> > Can you please also translate it to English ? 
> > Can you guys work together on this ? 
> > 
> > I can edit it as well, after you are done translating it. 
> > After me, may be John can can do a final round of editing ? ;*) 
> > 
> > rudi (ETL) 
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> > www.asics.ws   - Solutions for your ASIC needs - 
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