Hi All,
Can any one please help me out? I need Guidance from someone who has some experience in FPGA-based Synthesis and PNR:
I am woking on a fairly large SoC design coded in verilog, which has to be ported onto FPGA (Xilinx-VirtexE device) for testing purposes. Right now, I am able to get it working at 15MHz only-- with the typical FPGA utilisation being 80%. This limitation on frequency is due to the multi cycle paths and the false paths in the design, which have been identified in the ASIC synthesis. Now, I have to run the PNR for the design with the multicycle paths defined in the UCF. Can any one help me out by giving me some direction? I tried to use FROM THRU TO on a TNM property but that is not working as I want it to be. I feel it has taken False paths through a TIG but it is not treating a path as multi-cycle path, even after I constrained it to a delay of twice the master clk in my design. For example, consider the Time specification as given below:: MST_CLK is the master clock and the NET groups MCPATH_START and END have been suitably defined with TNM.
TIMESPEC "TS_MCPATH" =FROM "MCPATH_START" TO "MCPATH_END" "TS_MST_CLK" * 2;
Kindly correct me if I am wrong in my way of specifying the timespec. If I am not clear in my question, please let me know.
Thank you All in advance.
R Ramakrishna
ME (Digital Systems)