[oc] xilinx vhdl

[ckh827@hotmail.com]

HI, I have a question about the VHDL library.  How do I put my
function into a library, either IEEE or Work.  I'm using Xilinx
Webpack 4.2.  I can't find the location of "ieee.std_logic_1164.all;"
 because  one of my function generate too many "slices" and "LUTs" and
causes it can't be implemented.  I can use "package" and "component"
to combine every other .vhd files.  However, it cannot detect my
function even I do the same way.

I currently put my function in the same file.  If I just call the
function from IEEE library, I think it will solve the problem because
it will not implement the function in the library, is that right?  
However, if it is compiled to library WORK, would it affect the slices
and LUTs?  Is there any way to minimize the slices in the chip in this
case? It's about 40% increase in slices with this extra code in the file. 

I include the vec2int instead of int2vect function due to the size of
the code.  When I use it at another file, I put use work.veclib.all.
Anyway the format I used is,

library ieee;
use ieee.std_logic_1164.all;

package veclib is
  function vec2int(vec1: bit_vector)
	return integer;
  function int2vec(int1, NBits:integer)
	return bit_vector;
end veclib;

package body veclib is

function vec2int(vec1: bit_vector)
  return integer is

  variable retval: integer := 0;
  alias vec: bit_vector(vec1'length - 1 downto 0) is vec1;

  begin
    for i in vec'high downto 1 loop
      if (vec(i) = '1') then
	retval := (retval + 1) * 2;
      else
	retval := retval + 1;
      end if;
  end loop;

  if vec(0) = '1' then retval := retval + 1;
  end if;
	return retval;
end vec2int;
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