[oc] re: query regarding Xilinx PAR

["Stanford, David" <STANFDA@mail.northgrum.com>]

I use the Xilinx Foundation tools instead of the EDA tool so the answer may
be different. 
However, I typically route my designs a time or two without timing
constraints before
adding in the constraints (besides clocks). It's always frustrating to do a
long place
and route and then find out that something failed to meet the timing
constraints that you
had designated. It's also not easy (for me) to find multi-cycle paths or
false paths 
that need to be designated in the constraints file. 

My educated guess is that you'd use that option when you wanted to get a
successful route, 
or you didn't want your timing constraints, which may be too tough to meet,
to hold up a 
route. 

David Stanford
Design Engineer
Northrop Grumman
Rolling Meadows, IL

 cores@opencores.org	 cores-digest V1 #497
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From: harshit.suri@st.com
Date: Tue, 19 Feb 2002 09:42:48 +0530
Subject: [oc] A Query Regarding Xilinx PAR

     Hello Everyone..I am working on EDA development and am interested to 
     know WHEN DOES a designer(user of the Xilinx FPGA EDA tool) ,use the 
     "ignore timing constraints" option in the xilinx design flow.I want to 
     know why and when would he use this option in the design tool,inspite 
     of him specifying timing constraints..I would be happy if i could get 
     a broad spectrum of answers from all the designers out there so that i 
     could understand this issue better..
     
     Best Regards 
     Harshit Suri

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