[oc] Risc5x update

["MikeJ" <mikej@opencores.org>]

Igor, 

well spotted, I misread the data sheet there !
I've uploaded rel 1.1 and more extensive test code.

Damjan, do you have an idiots guide to uploading a new project to CVS?
I would like to get the core under source control.

Thanks a lot,
Mike.
----- Original Message ----- 
From: "Igor Sokolov" <xilirus@inbox.ru>
To: <mikej@opencores.org>
Sent: Monday, February 11, 2002 2:23 PM
Subject: Risc5x


> Hi, Mike!
> 
> Question is so:
> 
>   -- *********** REGISTER FILE Addressing ****************
>   p_addr_dec_comb : process(inst_fsel,status,fsr)
>   begin
>     if (inst_fsel = ("00" & INDF_ADDR)) then
>       fileaddr_indirect <= '1';
>     else
>       fileaddr_indirect <= '0';
>     end if;
> 
>     fileaddr_mux1 <= fsr(6 downto 0);
> (***)    fileaddr_mux0 <= (status(6 downto 5) & inst_fsel);
>   end process;
> 
> on line(***) shoud fileaddr_mux0 <= (status(6 downto 5) & inst_fsel)
>                 or fileaddr_mux0 <= (FSR(6 downto 5) & inst_fsel)???
> Thanks,Igor
> 
> 
> 

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml