[oc] =?gb2312?B?UmU6UmU6IFtvY10gRFBMTA==?=

["ganlu" <lu-gan@263.net>]

>
>
>----- Original Message ----- 
>From: haoguang.guo@p...  
>To: cores@o...  
>Date: Thu, 15 Nov 2001 09:58:20 +0800 
>Subject: Re: [oc] DPLL 
>
>> 
>> 
>> Hi, 
>>           I have a problem about  bit synchronization when use 
>> QPSK in satellite communication. When design the demodulator , how 
>> can i get the 
>> bit clock?  Some one said because of the fading and unknown delay , 
>> you can not synchroniza to the transmitter . so must  use the 
>> equalizer to estimate the channel. Is it right? 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> 
>> "Sam Gladstone"

@opencores.org on
>> 11/15/2001 06:29:28 AM
>>
>> Please respond to cores@o...
>>
>> Sent by: owner-cores@o...
>>
>>
>> To:
>> cc: (bcc: Haoguang Guo/SHA/SC/PHILIPS)
>> Subject: Re: [oc] DPLL
>> Classification:
>>
>>
>>
>> I take it you are demodulating back to a certain softbit size?
>> There is several books out there that are pretty good. I will find
>> the
>> one I used when we were writing an 802.11a phy for a company.
>>
>> The main idea is to demodulate each dimension of the
>> QPSKconstellation data
>> seperately by
>> breaking the real and imaginary up into two seperate demodulations.
>> Linear
>> extrapolations can be used to generate softbits for a first order
>> method.
>> There are more cost effective, but
>> harder to understand methods available as well.
>> (Assuming that you have already done the proper power and phase
>> corrections.)
>> I think the number of softbits generated looks like this table.
>> BPSK - 1 softbit per constellation
>> QPSK - 2 softbits per constellation
>> QAM-16 - 4 softbits per constellation
>> QAM-64 - 6 softbits per constellation
>> (QAMs get nasty because they are like combinations of different
>> codings that
>> have
>> to have multiple softbits generated per demension because of grey
>> coding
>> with the
>> modulution module. Yuck! )
>>
>> I will try to find the book name and send it out.
>>
>> Regards,
>> Sam
>>
>> ----- Original Message -----
>> From:
>> To:
>> Sent: Wednesday, November 14, 2001 9:24 AM
>> Subject: [oc] DPLL
>>
>>
>> > Hi,
>> >
>> > I take the liberty disturbing you.
>> > I am a friend from Taiwan.
>> > After reading your posts on Web, I know you are a professional
>> > communication designer.
>> > Now I am designing QPSK demodulator for wireless Lan with
>> verilog.
>> > Where can I find more helpful material, such as verilog code
>> for DPLL.
>> > Please kindly to give me some advice.
>> > Thank you a lot!
>> >
>> >
>> >
>>
>--
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>
I am stud.of china. I am insteresting about bit synchroniza
in digital communcation. I think maybe carrier is synchronized.
is condition. I want to knew about principle and how can realize it
in fpga(use vhdl or verilog). any helpflp is needed.
thank you

lu






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