RE: [oc] Low power design

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Frank,

I have received a mailer from Xilinx about the new CoolRunner II CPLDs they have
just launched. Do you think these might be of benefit to Jamil?

http://www.xilinx.com/cr2/introduction 

Paul


> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Frank Poppen
> Sent: 17 January 2002 09:06
> To: cores@opencores.org
> Subject: Re: [oc] Low power design
> 
> 
> Hello Jamil,
> 
> you should have a look at our Website www.lowpower.de
> Their is a special paper I wrote: "Low Power Design Guide"
> I went through all the books on low power design I found and put together
> the main points there.
> 
> Best regards,
> Frank
> 
> Jamil Khatib wrote:
> > 
> > In my bluetooth core design I have to support low power operation modes.
> > 
> > Is there any suggestion for low power design?
> > 
> > In bluetooth some internal blocks such as (Tx & Rx data path) can be
> > disabled. Is it recommended to use gated clocks? In FPGA gated clocks
> > produces consume large hardware resources.
> > 
> > Do you have any recommendation for me?
> > 
> > Note: system clock is less than 20MHz
> > 
> > Thanks
> > --
> >    Jamil Khatib
> > OpenCores Organization
> > http://www.opencores.org
> > 
> > --
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> 
> 
> -- 
> Dipl.-Inform. Frank Poppen | We use the freshest handpicked electrons
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