Re: [oc] Binary Divides for uP core

[Rudolf Usselmann <rudi@asics.ws>]

On Tuesday 15 January 2002 04:30 am, Paul McFeeters wrote:
> Hi,
>
> Does anybody know the routine for doing a binary division in HDL?
> I'm developing a uP core and would like to do divisions in one
> clock cycle if possible? The multiple instruction was easy to
> figure out but I'm still stuck on the division one.

Hmm, what technology are you targeting ? ASIC ? 0.5 or 0.1 micron ? FPGA ?
How large are your operands ? 8 bits ? 32 bits ? 64 bits ?
How large is your clock cycle ? 100 nS ? 1 ms ? 1 sec ?

rudi

>
> Paul
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