[oc] 8051 Verilog core

[akfoo_uk@hotmail.com]

Hi:
I'm recently using Modelsim simulator for the Verilog 8051 core 
of "Opencores" project, but I can't fully compile it cause of the "define" 
library (eg: ALU module). May I know what is the simulator used for this 
design core?
:-).

Best regard,
Alex Au

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml