Re: [oc] A 'core server' ?

["Marko Mlinar" <markom@opencores.org>]

> Before I embark on this non-trivial project, does
> anyone have a better solution, or know of an
> existing GPLed product which is similar?
I think we should use GPLed product for this kind
of compiler, or get a sponsor. It would be the best,
if we can include binaries in the core package.

But why don't you use C?

Maybe the problem with this generators is that not enough
people knows them, and they significantly reduce open.
Maybe nobody will use it if it cannot be built in the first try.

Another possibility, I can think of is to add some primitives
to VHDL and Verilog, that could build the right source.
I suppose you need something like

`repeat WIDTH

`endrepeat

or
`define WIDTH 3
`while WIDTH <= 5
wire test_##WIDTH = WIDTH == 3;
`endwhile

resulting
wire test_3 = 3 == 3;
wire test_4 = 4 == 3;
wire test_5 = 5 == 3;

I can generate such precompiler for you, but first we need to
figure out.
Is this solution sufficent for you?
Have in mind that we can define really powerful construct such as:
`assign WIDTH DEBUG?32:(USER_WIDTH+1)
Thus giving us almost full power of C, except subroutines.

Marko


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