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Hi,everyone,i am ssy,i have previous post a message in this board announce
that i am developing a arm compatible processor,i will describ my idea
below:
first ,i must apologize that i have miss my name in the mail
my name is ShengYu Shen from the National University of Defence
Technology,i am struggle for my Phd.when i am study for my master degree,one of
my course is ARCHITECTURE: a quantity perspective,aince then i want to design my
own microprocessor
i will describ my idea below:
first,i want to design a GENERAL microarchitecture that can be
synthesize,the general means that you can make minor change to it to run varias
risc instruction sets,range from arm to mips ,even powerpc or alpha.so,i think
that the patent will not be a question.i think almost all the change are in the
decoder and reorder buffer,because after the decoder generate the micro
instruction to run in the tomasulo structure,all thing is almost the same.
second,because i want to devote to the design of the pipeline structure of
the chip,i want help on datapath(especialy on highly pipelined multipler) and
the cache ,and the memory interface,and DMA.i have write the behavior model of
the memory and cache controller,but i know that they can not be synthesize and
they are highly depende on the ASIC library,at the same time,i am not very sure
that the description is correct
third,except the chip,i still need many many thing to run my system up,from
mouse controller to operate system,i still do not have idea on it,
by the way, because some reason i do not know,the email account of my own
that have been aply for ONE YEAR ago have not been given to me,i am still using
the email address of my director skli@nudt.edn.cn
all code is in VERILOG,because i have forget the complex style of
VHDL.
and i am busy in design this chip and some other bussinees,i am sorry that
you can not visit the website you want within a short time,but there will
certainly be such a site in this year. |