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We are http://www.si2.org and people talk about us http://www.si2.org/OLA/industrytestimonials.htmI
because we have done (projects, OLA) http://www.isdmag.com/editorial/2000/standards0012.html
So, we have bent the EDA tools industry around to
this way of thinking, because it solves problems. Get the right answer the
first time (no more 'third time's a charm', no more 'what's my wife's name
again'). Get real numbers as technology gets smaller (lambda
dimension). IBM, Cadence, Synopsys, Mentor, ... So, now there are
various pre-release tools (PKS, PC, ...), that EDA tools vendors want to make
money on (~$300k/seat/yr).
I wonder if these tools, in their current state of
development, really work (anybody got a real test case, that doesn't need
debugging, that we could run through this tools set all the way to we'll
produce actual silicon to see if it wiggles).
I have until the end of April to come up with some
'test cases'. I, probably, ought to have of range of these things, from
the small to the large, from the simple to the complex. Each case needs to
have an entire documentation set (source Verilog at either RTL or structural
[gate] level, a Verilog test bench that wiggles 'everything', a written text
description of what it is and how it works) and a point of contact (who do I
call in the middle of the night when we figure out it isn't working), WHERE
EVERYTHING IS KNOWN GOOD. Also, it needs to be public domain, because it
will be demonstrated at DAC in June, and just everybody is going to want a copy
to take it home and try on their flow and process in order to compare
efficiency/sufficiency.
You wouldn't know of anybody that could be
interested, do you?
B. Keith Peshak
Silicon Integration Initiative, Inc
4030 West Breaker Lane, Suite 550
Austin, Texas 78759
512-342-2244 ext. 20
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