Re: [oc] SoC bus review

[Rudolf Usselmann <rudi@asics.ws>]

on 1/3/01 14:11, John Dalton at johnd@southern-poro.com wrote:

> 
> Damjan Lampret wrote:
>> How about scan chain for ASIC verification.
> 
> Possibly.  I'm not sure a scan chain belongs in a "SoC
> bus" specification in the usual sense of the word.  Could
> putting JTAG into a SoC bus spec limit choice of testing
> methodology?  What happens if someone uses (or invents)
> a non-JTAG based test method?

Well, here is a suggestion:

We could look at various options and choose the preferred one.
In a spec (SoC or other) we would state that the preferred option
is X, but the final call is up the developer (omit altogether or
do something else) ...

rudi

> How about another level of specification above
> the "SoC bus", which includes an "SoC bus" and a test
> interface? (Use a fixed width font to see the ASCII art.)
> 
> LEVEL x                 LEVEL x+1
> 
> SoC interface  ---|--- SoC uP type bus (wishbone, AMBA, CoreConnect, etc.)
> |
> |--- Test bus (JTAG, etc.)
> 
> And taking a slightly wider view
> 
> LEVEL x-1                      LEVEL x
> 
> FPGA Module Standard  ---|--- SoC interface (as above)
> |
> |--- Power Supply Bus
> 
> 
> 
>