Re: [oc] Modular FPGA Board: Block Diagram

["Richard Herveille" <Richard.Herveille@pie.nl>]

Hmm, I seem to be missing something. You want to connect memory directly to
the PCI bus ?? Or do you want to use either memory (and no pci) or pci (and
no memory) ?

Both seem almost impossible to do; PCI specs are very strict.
1) Trace length:
- max. trace length for all 32bit signals are limited to 1.5 inch.
- max. length for additional signals used in 64bit extensions are limited to
2inch.
- max. length for PCI CLK signals is 2.5 inch.
2) Impedance:
- Z0 (characteristic impedance) must be 60-100ohm
- trace velocity must be 150-190ps/inch
3) Load:
- Shared PCI signals (eg EDx) must be limited to 1 load

The trace length limit requires placing the FPGA close to the edge
connector. This implies placing the simm connector behind/above the FPGA.
Here is our next problem. The PCI bus is based on first reflective wave
switching (not incident wave). This means the signals is placed mid-level at
the bus(1.6V for 3.3V designs, 2.5V for 5V designs) and reflects at the end
of the line (in this case the simm-connectors). The reflection generates the
1.6->3.3V/ 2.5-5V step. This reflection has to traverse back and at some
point will reach the FPGA (but to late.)

Correct me if I am wrong

Richard Herveille