Re: [oc] miniUART VHDL errors in XIlinx Foundation series

["Ovidiu Lupas" <olupas@opencores.org>]

> In the information on the miniUART core, it is claimed that it's been
> sucessfully used with the XIlinx Foundation Series 2.1i. However,
> serveral errors and warnings occur when attempting to simulate, or even
> just from running "Check Syntax". Among them are:
>
> UART_lib.vhd:
> Warning: Initial values for signals are not supported for
> synthesis.
Of course ! But I had to simulate the design. So, you have to comment
those lines. In fact, the UART_lib contains only a conversion function which
NOT need to be synthesized ...

> uarttest.vhd:
> Warning: Initial values for signals are not supported for
> synthesis.
> Error: "Time" is an unsupported type on line 0
> Error: This form of wait statement is not supported for synthesis
> on line 148. ("wait for 5 ns")
UARTtest is the testbench to test the UART and you are NOT supposed to
synthesize it !

> Can anyone offer any information on how these warnings/errors can be
> reconciled with the fact that it has worked successfully for the author?
I guess that me, the author, would make the best option ...

> As a minor issue, what is the rationale for putting the small UART_Def
> package in a file with a different name (uart_lib)?
... no comments ...

regards,
  Ovidiu Lupas