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I am Motohiro Kurisu, director of Hirotech, Inc in
Japan.
My company has been made IPs almost three years
and
have sold them to the U.S. companies such as Zilog and
TeleCruz.
Last November, I made an open source code of my
scalable
RISC engine which covers 8bits, 16bits and 32bits
instruction
as well as 64bits. I had a patent for this architecture
in the
U.S.. It uses modified harvard architecture, combine
two
instructions in one cycle, change the instruction
implementation
width. So the same instruction can be used for 8, 16, 32
and 64bits.
The article and source code are published on one of Japanese
magazine twice. I am going to release 32 bits engine one
or two
months later. I have two customers right now, I just
released
beta version to one customer. It uses Xilinx
XCV300 device
and runs about 30MHZ. 16 bits one is a little higher,
33-35MHZ.
I have heard that your organization is doing same thing and I
hope I can work with your organization if it is
possible. I know
the source code should be open for market because they
have
a different platform for develop environment. They want
to check
it in FPGA very quick and source code is needed.
My company has RISC engine core designed for
network application,
graphics co-processor, and
tiny 8 bit machine. We also have TS-DMUX
module for digital TV, pixel OSD for TV micro, 8251, UART,
PWM,
I..R. capture, HDTV memory controller. I am not sure
which one
should be open but RISC engine is open now.
Hope someone is interested in my project and can
work together.
My RISC engine aims at embedded solution, not PC
applicaion.
I did not know your organizaion well so I did it
in Japan at first, soon,
same article is published in Korea.
Rgds,
Motohiro Kurisu
Hirotech, Inc.
17-6 minami Fujisawa
Fujisawa city, Kanagawa-ken
Japan 251-0055
phone 81-466-28-1171
fax 81-466-29-6820
www.hirotech.com (only
Japanese)
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