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>Architecture names should be
entity names followed by 3 letter suffix "beh" for behavioural
description, "rtl" for rtl
>description or "str" for structural description. This sounds a little redundant to me.
The architecture usually is :
architecture ArchName of EntityName is
So, the entity name always appears in the arch
decl. I think more appropiate to name :
architecture Behavioural of EntityName
is
architecture Structural of EntityName
is Of course, all this are from VHDL point of view...
;-)
In Verilog, I have no clue.
regards, Ovidiu
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