head 1.4; access; symbols REL:1.1.1.1 PALEY:1.1.1; locks; strict; comment @# @; 1.4 date 2005.11.19.15.18.55; author mgeng; state Exp; branches; next 1.3; commitid 1aa0437f42514567; 1.3 date 2005.11.05.10.45.12; author mgeng; state Exp; branches; next 1.2; commitid 2091436c8d324567; 1.2 date 2005.10.12.19.38.43; author mgeng; state Exp; branches; next 1.1; commitid 1777434d663a4567; 1.1 date 2003.01.14.21.49.57; author rpaley_yid; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.01.14.21.49.57; author rpaley_yid; state Exp; branches; next ; desc @@ 1.4 log @rnw replaced by nce, nwe and noe, tristate drivers added @ text @

Description of single_port memory and test environment.

Abstract:

A VHDL simulation model for an asynchronous static single port memory is described. The memory is implemented as three different architectures, a simple one and 2 ones which are optimized for efficient use of simulator memory. Data and address buses are unconstrained, so multiple instances with different address and data bus widths can be implemented in one single design. A testbench is also provided.

Port Interface:

Port Name

Type

Description

rnwtQ

Time

Time delay until data or tristate appears on q data bus.

d

 STD_LOGIC_VECTOR

Input data bus, unconstrained

q

STD_LOGIC_VECTOR

Output data bus, unconstrained

a

STD_LOGIC_VECTOR

Address bus, unconstrained

nce

STD_LOGIC

not chip enable
nwe
 STD_LOGIC
 not write enable
noe
 STD_LOGIC
 not output enable

dealloc_mem

BOOLEAN

When set to true, deallocate linked list memory.

Functional Description:

All 3 architectures functionally behave like commercially available asynchronous SRAMs if you connect d and q to the same bus. If a memory location is read which was not written to during the current simulation, 'U's are loaded onto the memory bus.

nce
 nwe
 noe
 d
 q
 Mode
1
 don't care
 don't care
 don't care
 high Z
 deselected
0
 1
 1
 don't care
 high Z
 output disabled
0
 0
 don't care
 input data
 high Z
 write
0
 1
 0
 don't care
 RAM content
 read

Architecture ArrayMemNoFlag

This architecture implements the memory core as an array of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided for comparison with the models below but not recommended for use in your design.

Architecture ArrayMem

This architecture implements the memory core as an array of BIT_VECTOR. This arrangement allows less workstation memory to be used than the ArrayMemNoFlag architecture. Use this architecture if most addresses in the simulated memory are written at least once.

Architecture LinkedList

This architecture implements the memory core as a linked list of arrays of BIT_VECTOR. Each array in the linked list is a page of memory whose size is specified with the constant PAGEDEPTH in the package linked_list_mem_pkg. This arrangement allows less workstation memory to be used than either the ArrayMemNoFlag or ArrayMem architectures because memory representing the array data is only allocated if the memory is actually written to. To de-allocate the memory in the linked list, set dealloc_mem to true. A short pulse is sufficient. Use this architecture if a significant portion of your simulated memory (which need not be contiguous) is never written to.

Example Timing:

Clearing both nce and nwe to to '0' immediately causes a write operation. Changing the address while nce and nwe are asserted causes a write to the new address, too (But don't do that with real RAMs because you could destroy more memory locations while the address bus settles). Every read (and tristate) operation is delayed rnwtQ ns. The below sample timing diagram illustrates both a read and write operation.

Timing diagram

Testbench Description:

The test bench is arranged as a client server architecture as specified by Bergeron1. A diagram illustrating the testbench is given below.

Testbench schematic  
Two tests are specified in tc_single_port component. The first test writes data to two logical memory pages, and then reads them back verifying the correct data. The test case writes an error message to the console for every miscompare. The second case verifies that the single_port memory model outputs unknowns to the q bus if a read occurs for an unwritten memory location. Six configurations are specified in the test bench architecture tb_single_port, running both tests for each single_port architecture.

Usage:

A Makefile is used to compile and run all of the tests in a Unix or like environment, such as Cygwin. The compilation and simulation is targetted to the SymphonyEDA tool available at www.symphonyeda.com.

The source files and Makefile are located in {top}/VHDL

To compile: make com

To simulate all of the tests: make sim

To clean the compiled library: make clean

The tests are labeled :

To simulate any of these tests, type make {testname}

Please contact Robert Paley at rpaley_yid@@opencores.org or Michael Geng at vhdl@@michaelgeng.de if you have any questions or comments.

1Writing Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – ISBN 0-7923-7766-4




@ 1.3 log @Constant PAGEDEPTH moved from single_port_pkg to linked_list_mem_pkg because it's only used in the linked list implementation @ text @d4 1 a4 1 d8 1 a8 1 d10 1 a10 1 d12 1 a12 1 d14 1 a14 1 d16 1 a16 1 d18 1 a18 1 d32 1 a32 1 d34 1 a34 1 d36 2 a37 2 of single_port memory and test environment. d39 9 a47 9

A VHDL simulation model for an asynchronous single port memory is described. The memory is implemented as three different architectures, a simple one and 2 ones which are optimized for efficient use of simulator memory. Data and address buses are unconstrained, so multiple instances with different address and data bus widths can be implemented in one single design. A testbench is also provided.

d49 6 a54 5 d170 1 a170 1 d172 123 a294 21

The first architecture is called ArrayMemNoFlag, and implements the memory core as an array of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided for comparison with the models below but not recommended for use in your design.

The second architecture is called ArrayMem, and implements the memory core as an array of BIT_VECTOR. This arrangement allows less workstation memory to be used than the ArrayMemNoFlag architecture. Use this architecture if most addresses in the simulated memory are written at least once.

The third architecture is called LinkedList, and implements the memory core as a linked list of arrays of BIT_VECTOR. Each array in the linked list is a page of memory whose size is specified with the constant PAGEDEPTH in the package linked_list_mem_pkg. This arrangement allows less workstation memory to be used than either the ArrayMemNoFlag or ArrayMem architectures because memory representing the array data is only allocated if the memory is actually written to. To de-allocate the memory in the linked list, set dealloc_mem to true. Use this architecture if a significant portion of your simulated memory (which need not be contiguous) is never written to.
d296 2 a297 22 All 3 architectures are asynchronous and triggered with any change of d, a or rnw (and dealloc_mem for the LinkedList architecture). When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U's are loaded onto the memory bus.

Functional Timing:

The single port memory is asynchronous and is triggered on any change of d, a or rnw. When rnw is cleared to '0', the write occurs at the same time as rnw'transaction. When a read occurs, with rnw = '1' , data appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample timing diagram illustrates both a read and write operation.


d299 1 a299 1 d301 1 a301 1 by Bergeron

Two tests are specified in tc_single_port component. The first test writes data to two logical memory pages, and then reads them back verifying the correct data. The test case writes an error message to the console for every miscompare. The second case verifies that the single_port memory model outputs unknowns to the q bus if a read occurs for an unwritten memory location. Six configurations are specified in the test bench architecture tb_single_port, running both tests for each single_port architecture.

d318 1 a318 1 d320 2 a321 2 environment, such as Cygwin. The compilation and simulation is targetted to the SymphonyEDA tool available at To compile: make com

d329 2 a330 2

d332 1 a332 1 d334 1 a334 1 d336 11 a346 11
  • ll_error
  • ll_main
  • mem_main
  • mem_error
  • memnoflag_main
  • memnoflag_error
    • d348 1 a348 1 d350 1 a350 1 d352 4 a355 4 or Michael Geng at     vhdl@@michaelgeng.de if you have any questions or comments.

    d358 4 a361 3 Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – ISBN 0-7923-7766-4

    @ 1.2 log @Buses unconstrained, triggered not only with rnw but also with address and data bus transactions @ text @d4 1 a4 1 d8 1 a8 1 d10 1 a10 1 d12 1 a12 1 d14 1 a14 1 d16 1 a16 1 d18 1 a18 1 d32 2 d35 1 a35 3

    Description d37 1 a37 1 d39 9 a47 9

    A VHDL simulation model for an asynchronous single port memory is described. The memory is implemented as three different architectures, a simple one and 2 ones which are optimized for efficient use of simulator memory. Data and address buses are unconstrained, so multiple instances with different address and data bus widths can be implemented in one single design. A testbench is also provided.

    d49 1 a49 1 d51 1 a51 1

    d55 2 a56 2 d134 1 a134 1 d136 29 a165 27

    The first architecture is called ArrayMemNoFlag, and implements the memory core as an array of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided for comparison with the models below but not recommended for use in your design.

    The second architecture is called ArrayMem, and implements the memory core as an array of BIT_VECTOR. This arrangement allows less workstation memory to be used than the ArrayMemNoFlag architecture. Use this architecture if most addresses in the simulated memory are written at least once.

    The third architecture is called LinkedList, and implements the memory core as a linked list of arrays of BIT_VECTOR. Each array in the linked list is a page of memory whose size is specified in single_port_pkg. This arrangement allows less workstation memory to be used than either the ArrayMemNoFlag or ArrayMem architectures because memory representing the array data is only allocated if the memory is actually written to. To de-allocate the memory in the linked list, set dealloc_mem to true. Use this architecture if a significant portion of your simulated memory (which need not be contiguous) is never written to.

    All 3 architectures are asynchronous and triggered with any change of     d, a or rnw (and dealloc_mem for the LinkedList architecture). When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U's are loaded onto the memory bus.
    d167 7 a174 7

    The single port memory is asynchronous and is triggered on any change of d, a or rnw. When rnw is cleared to '0', the write occurs at the same time as rnw'transaction. When a read occurs, with rnw = '1' , data appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample timing diagram illustrates both a read and write operation.

    d177 3 a179 3

    d181 7 a187 7

    The test bench is arranged as a client server architecture as specified by Bergeron1. A diagram illustrating the testbench is given below.

    Two tests are specified in tc_single_port component. The first test writes data to two logical memory pages, and then reads them back verifying the correct data. The test case writes an error message to the console for every miscompare. The second case verifies that the single_port memory model outputs unknowns to the q bus if a read occurs for an unwritten memory location. Six configurations are specified in the test bench architecture tb_single_port, running both tests for each single_port architecture.

    d200 6 a205 5

    A Makefile is used to compile and run all of the tests in a Unix or like environment, such as Cygwin. The compilation and simulation is targetted to the SymphonyEDA tool available at www.symphonyeda.com.

    d207 3 a209 3
    To compile: make com

    d211 2 a212 2

    d214 1 a214 1 d216 1 a216 1 d218 11 a228 11
  • ll_error
  • ll_main
  • mem_main
  • mem_error
  • memnoflag_main
  • memnoflag_error
    • d230 1 a230 1 d232 6 a237 6

    Please contact Robert Paley at rpaley_yid@@opencores.org or Michael Geng at vhdl@@michaelgeng.de if you have any questions or comments.

    d239 5 a243 4 class="sdfootnotesym" name="sdfootnote1sym" href="#sdfootnote1anc">1Writing Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – ISBN 0-7923-7766-4

    @ 1.1 log @Initial revision @ text @d4 1 a4 1 d8 1 a8 1 d10 1 a10 1 d12 1 a12 1 d14 1 a14 1 d16 1 a16 1 d18 1 a18 1 d31 4 a34 2

    B"H

    d36 2 a37 1 of single_port memory and test environment.     d39 9 a47 2

    A single port memory with testbench is described. The memory is implemented as three different architectures.

    d49 1 d51 1 a51 1 d55 2 a56 2 d134 1 d136 28 a163 30

    The single_port memory is implemented as three different architecures. The first architecture is called ArrayMemNoFlag, and implements the memory core as an array of STD_LOGIC_VECTOR. The memory is asynchronous and triggered on rnw'transaction. When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U' are loaded onto the memory bus.

    The second architecture is called ArrayMem, and implements the memory core as an array of BIT_VECTOR. This arrangement allows less workstation memory to be used than the ArrayMemNoFlag architecture. The memory is asynchronous and triggered on rnw'transaction. When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U' are loaded onto the memory bus.

    The third architecture is called LinkedList, and implements the memory core as a linked list of arrays of BIT_VECTOR. Each array in the linked list is a page of memory whose size is specified in single_port_pkg. This arrangement allows less workstation memory to be used than either the ArrayMemNoFlag or ArrayMem architectures. The memory is asynchronous and triggered on rnw'transaction. When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U' are loaded onto the memory bus. To de-allocate the memory in the linked list, set dealloc_mem to true.

    d165 8 a172 5

    The single port memory is asynchronous and is triggered on rnw'transaction. When rnw is cleared to '0', the write occurs at the same time as rnw'transaction. When a read occurs, with rnw = '1' , data appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample timing diagram illustrates both a read and write operation.

    d174 4 a177 2 width="958" height="251" border="0">

    d179 18 a196 16

    The test bench is arranged as a client server architecture as specified by Bergeron1. A diagram illustrating the testbench is given below.


    Two tests are specified in tc_single_port component. The first test writes data to two logical memory pages, and then reads them back verifying the correct data. The test case writes an error message to the console for every miscompare. The second case verifies that the single_port memory model outputs unknowns to the q bus if a read occurs for an unwritten memory location. Six configurations are specified in the test bench architecture tb_single_port, running both tests for each single_port architecture.

    d198 5 a202 4

    A Makefile is used to compile and run all of the tests in a Unix or like environment, such as Cygwin. The compilation and simulation is targetted to the SymphonyEDA tool available at www.symphonyeda.com .

    d204 3 a206 2
    To compile: make com

    d208 2 a209 1

    d211 1 d213 1 d215 11 a225 10
  • ll_error
  • ll_main
  • mem_main
  • mem_error
  • memnoflag_main
  • memnoflag_error
    • d227 1 d229 1 d231 1 d233 2 a234 1
    d237 1 a237 1 Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – d239 3 a241 1
    @ 1.1.1.1 log @initial checkin @ text @@
    d56 3 a58 2 d60 3 a62 2 d64 6 a69 5
    d71 3 a73 2 d75 9 a83 7

    Time delay from rnw = read until data appears on q data bus.
    d85 5 a89 4 STD_LOGIC_VECTOR
    		 d91 5 a95 4
    d97 3 a99 2 d101 4 a104 3

    		d106 5 a110 4
    d112 3 a114 2 d116 4 a119 3

    		d121 9 a129 7

    rnw

    		 d131 25 a155 7

    Read not write port
    d157 3 a159 2 d161 3 a163 2 d165 4 a168 4
    d58 2 a59 2 d61 5 a65 5
    d67 2 a68 2 d70 2 a71 2 d73 4 a76 4
    d78 4 a81 4 STD_LOGIC_VECTOR
    		 d83 4 a86 4
    d88 2 a89 2 d91 3 a93 3

    		d95 4 a98 4
    d100 2 a101 2 d103 3 a105 3

    		d107 4 a110 4
    d112 2 a113 2 d115 2 a116 2 d118 4 a121 4
    d123 2 a124 2 d126 2 a127 2 d129 4 a132 4
    d58 2 a59 2 d61 5 a65 5
    d67 2 a68 2 d70 2 a71 2 d73 4 a76 4
    d78 9 a86 10

    data_inter_typ

    Input data bus, type specified in single_port_pkg
    d88 11 a98 10

    data_inter_typ

    Output data bus, type specified in single_port_pkg
    d100 11 a110 10

    addr_inter_typ

    Address bus, type specified in single_port_pkg
    d112 2 a113 2 d115 2 a116 2 d118 4 a121 4
    d123 2 a124 2 d126 2 a127 2 d129 4 a132 4