head 1.1; access; symbols; locks; strict; comment @# @; 1.1 date 2008.03.10.16.27.04; author mcupro; state Exp; branches; next ; commitid 267f47d561404567; desc @@ 1.1 log @no message @ text @ #Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Mon Mar 10 17:41:12 2008 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved @@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v" @@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v" @@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v" @@I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v" @@I::"D:\LWRISC\RTL\sim_rom.v" @@I::"D:\LWRISC\RTL\test.v" @@I::"D:\LWRISC\RTL\mem_man.v" @@I:"D:\LWRISC\RTL\mem_man.v":"D:\LWRISC\RTL\clairisc_def.h" @@I::"D:\LWRISC\RTL\memory.v" @@I:"D:\LWRISC\RTL\memory.v":"D:\LWRISC\RTL\clairisc_def.h" @@I:"D:\LWRISC\RTL\memory.v":"D:\LWRISC\RTL\rom_set.h" @@I::"D:\LWRISC\RTL\risc_core.v" @@I:"D:\LWRISC\RTL\risc_core.v":"D:\LWRISC\RTL\clairisc_def.h" @@I::"D:\LWRISC\RTL\altera\rom512x12.v" @@N: : rom512x12.v(39) | Read directive translate_off @@N: : rom512x12.v(41) | Read directive translate_on @@N: : rom512x12.v(58) | Read directive translate_off @@N: : rom512x12.v(76) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\rom1024x12.v" @@N: : rom1024x12.v(39) | Read directive translate_off @@N: : rom1024x12.v(41) | Read directive translate_on @@N: : rom1024x12.v(58) | Read directive translate_off @@N: : rom1024x12.v(76) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\rom2048x12.v" @@N: : rom2048x12.v(39) | Read directive translate_off @@N: : rom2048x12.v(41) | Read directive translate_on @@N: : rom2048x12.v(58) | Read directive translate_off @@N: : rom2048x12.v(76) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\ram128x8.v" @@N: : ram128x8.v(141) | Read directive translate_off @@N: : ram128x8.v(143) | Read directive translate_on @@N: : ram128x8.v(169) | Read directive translate_off @@N: : ram128x8.v(184) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\rom32x12.v" @@N: : rom32x12.v(39) | Read directive translate_off @@N: : rom32x12.v(41) | Read directive translate_on @@N: : rom32x12.v(58) | Read directive translate_off @@N: : rom32x12.v(76) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\rom64x12.v" @@N: : rom64x12.v(39) | Read directive translate_off @@N: : rom64x12.v(41) | Read directive translate_on @@N: : rom64x12.v(58) | Read directive translate_off @@N: : rom64x12.v(76) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\rom128x12.v" @@N: : rom128x12.v(39) | Read directive translate_off @@N: : rom128x12.v(41) | Read directive translate_on @@N: : rom128x12.v(58) | Read directive translate_off @@N: : rom128x12.v(76) | Read directive translate_on @@I::"D:\LWRISC\RTL\altera\rom256x12.v" @@N: : rom256x12.v(39) | Read directive translate_off @@N: : rom256x12.v(41) | Read directive translate_on @@N: : rom256x12.v(58) | Read directive translate_off @@N: : rom256x12.v(76) | Read directive translate_on Verilog syntax check successful! File D:\LWRISC\RTL\sim_rom.v changed - recompiling @